The Samsung Semiconductor division is among the successful IC manufacturers and poised to overtake Intel as the world’s largest IC supplier. Yet, Samsung isn’t stopping here, the company has announced its future transistor nodes at the annual Samsung Foundry Forum. Samsung’s fabs were already the first to ship 10nm-class SoCs in the form of the Exynos 8895 and Snapdragon 830 and company now targets 4nm-class nodes by 2021.
The announcement includes six new nodes; a 8nm LPP node which would incorporate much of innovations from their current 10nm LPP process. This 8nm node will focus on performance and area (PPA) advantages, i.e. better perf/watt and perf/mm2 while being on par with TSMC’s N7 process. The node is already in risk production is set to be ready in late 2018 if yields are satisfactory and will eventually make its way in consumer devices in 2019. Next up are the new 7nm and 6nm LPP node which will be the first nodes built using Samsung’s second generation EUV (Extreme Ultraviolet) lithography, replacing the DUV/Argon-Fluoride lithography and triple patterning used in earlier 10/8nm devices. Both nodes will compete with TSMC’s CLN7FF+ process and are are set to enter risk production in late 2018 and 2019 respectively.
This achivement was made possible by the joint effort from Samsung and ASML. Samsung states that their current EUV techniques use a mere 250W of power and will thus counter the high costs to keep high-volume manufacturing (HVL) on track for early 2021 while achieving higher yields. According to Kelvin Low, senior director of foundry marketing at Samsung the “magic number” for productivity with EUV is 1,500 wafers per day and Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.