The Samsung Semiconductor division is among the successful IC manufacturers and poised to overtake Intel as the world’s largest IC supplier. Yet, Samsung isn’t stopping here, the company has announced its future transistor nodes at the annual Samsung Foundry Forum. Samsung’s fabs were already the first to ship 10nm-class SoCs in the form of the Exynos 8895 and Snapdragon 830 and company now targets 4nm-class nodes by 2021.
The announcement includes six new nodes; a 8nm LPP node which would incorporate much of innovations from their current 10nm LPP process. This 8nm node will focus on performance and area (PPA) advantages, i.e. better perf/watt and perf/mm2 while being on par with TSMC’s N7 process. The node is already in risk production is set to be ready in late 2018 if yields are satisfactory and will eventually make its way in consumer devices in 2019. Next up are the new 7nm and 6nm LPP node which will be the first nodes built using Samsung’s second generation EUV (Extreme Ultraviolet) lithography, replacing the DUV/Argon-Fluoride lithography and triple patterning used in earlier 10/8nm devices. Both nodes will compete with TSMC’s CLN7FF+ process and are are set to enter risk production in late 2018 and 2019 respectively.
This achivement was made possible by the joint effort from Samsung and ASML. Samsung states that their current EUV techniques use a mere 250W of power and will thus counter the high costs to keep high-volume manufacturing (HVL) on track for early 2021 while achieving higher yields. According to Kelvin Low, senior director of foundry marketing at Samsung the “magic number” for productivity with EUV is 1,500 wafers per day and Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.
Samsung is also planning to introduce a 5nm lineup in 2020, this will be the last node to use the FinFET structure and will focus on power efficiency which will translate into small dies and lower TDP for embedded devices. And lastly, the 4LPP (Low Power Plus) which will be Samsung’s next-gen node. It will be built around Samsung’s own proprietary Gate All Around FET, dubbed GAAFET (Multi Bridge Channel FET) and will make use of a Nanosheet-like structure. Not much is known about the FEOL/BEOL changes but we expect more details to come at a later date.
Cross-section of (a) FinFET, (b) nanowire, and (c) nanosheet. (Source IBM)
In addition, the technology giant unwrapped its second-generation FD-SOI at 18nm using immersion lithography. The company has incorporated RF, and embedded Magnetic Random Access Memory (eMRAM) and other IP capabilities to its existing FD-SOI technology for the automotive and IoT industry. This new node will debut in late 2019/early 2020 and will provide a cheaper alternative to the bleeding-edge but more expensive sub-10nm nodes.
The semiconductor industry has been pushing back Moore’s law by refining their transistor structure, from planar transistors to sub-10nm InGaAs multi-gate (FinFET) devices and the adoption of multiple patterning. Samsung is no different, the company aims to push the limits even further by introducing the first commercial GAAFET (Gate All Around FET) transistor technology. This new transistor structure is slated to replace FinFET devices in the long run as density and transistor scaling continues in the EUV era.
Samsung will be using a variant of the GAAFET structure for their 4nm LPP node.
However, even this is a stop-gap measure as MOSFET technology as we know it will hit its theoretical limits for scaling in the first half of the 2020s according to the latest International Technology Roadmap for Semiconductors report. — There is currently a lot of research into future transistor designs which would eventually supercede ‘tradition’ transistors. Technologies such as 2.5D integrated devices, quantum well semiconductors (QW III-V), carbon nanotubes/nanowires or 1-atom thick graphene devices will hopeful provide more breathing room for semiconductor companies
Source: Samsung Newsroom